Job Description:

Hands-on experience in SV/UVM. Must be able to independently own and drive the verification of a block/SS with minimal guidance and supportExtensive experience in IP/sub-system and/or SoC level verification based on SV/UVMExperience in Tesplan and TB development, execution of testplan using high quality constrained random UVM tests to hit coverage goals on timeShould be good with debug and exposed to all aspects of verification flow including GatesimsExperience with verification of ARM/RISC-V based CPU sub-systems or SoCsExpertise of protocols like AMBA, PCIe, DDR, HBM, UCIe, USB, EthernetExperience in EDA tools and scripting (Python, TCL, Perl, Shell), revision control Hg, Git