Job Description:

QualificationsProven track record of success in verification strategy development and execution for large SoC's, and signoff with coverage metricsHands-on knowledge of UVM methodology, System Verilog, C/C++Implement directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, and multi-CPU environmentsIn-depth understanding of networking standards, bus protocols, high-speed serial link protocolsExperience with CPU instruction set testing and cache coherent system testingKnowledge of verification IP and functional coverage techniquesExperience with gate-level simulations of delay annotated netlistsExposure to FPGA emulation and lab validationProject planning and execution and performing test strategy tradeoffs to achieve coverage and schedule targetsStrong leadership and experience building world-class verification teamsBS in Electrical Engineering or related + 13 years of experience, or MS + 11 years of experience, or Ph.D. + 8 years of experience