Job Description:

Position: Design Verification EngineerLocation: Austin, TX (Onsite)Duration: Long-termPosition Overview:12+ years of relevant experience in Verification.Experience with System Verilog and UVM.Deep understanding of constrained randomization and the development of efficient test suites.Work with DV team and designers to build verification environments.Working knowledge of C++.Good knowledge of memory subsystem, including interconnect, last-level cache, coherency.Familiarity of Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.Agility to work on multiple tasksprojects.